MELFA Accessible Registers
The accessible registers of this product are shown below. The I/O address of MELFA is specified by "register name" + "number". For details on the register, refer to the manual for each CPU.
List of Registers
|
Classification |
Register Name |
Register Type |
Notation |
Support Availability |
Remarks |
|---|---|---|---|---|---|
|
R16RT |
D |
WORD |
Decimal |
Available |
|
|
D |
BIT |
Decimal |
Available |
Bit specification |
|
|
M |
BIT |
Decimal |
Available |
|
|
|
SD |
WORD |
Decimal |
Available |
|
|
|
SD |
BIT |
Decimal |
Available |
Bit specification |
|
|
SM |
BIT |
Decimal |
Available |
|
|
|
U3En\G |
WORD |
Decimal |
Available |
|
|
|
U3En\G |
BIT |
Decimal |
Available |
Bit specification |
|
|
U3En\HG |
WORD |
Decimal |
Available |
|
|
|
U3En\HG |
BIT |
Decimal |
Available |
Bit specification |
|
|
X |
BIT |
Hexadecimal |
Available |
|
|
|
Y |
BIT |
Hexadecimal |
Available |
|
|
|
Q172DSR |
D |
WORD |
Decimal |
Available |
|
|
D |
BIT |
Decimal |
Available |
Bit specification |
|
|
M |
BIT |
Decimal |
Available |
|
|
|
SD |
WORD |
Decimal |
Available |
|
|
|
SD |
BIT |
Decimal |
Available |
Bit specification |
|
|
SM |
BIT |
Decimal |
Available |
|
|
|
U3En\G |
WORD |
Decimal |
Available |
|
|
|
U3En\G |
BIT |
Decimal |
Available |
Bit specification |
|
|
X |
BIT |
Hexadecimal |
Available |
|
|
|
Y |
BIT |
Hexadecimal |
Available |
|
|
|
CR800-D |
D |
WORD |
Decimal |
Available |
|
|
D |
BIT |
Decimal |
Available |
Bit specification |
|
|
SD |
WORD |
Decimal |
Available |
|
|
|
SD |
BIT |
Decimal |
Available |
Bit specification |
|
|
SM |
BIT |
Decimal |
Available |
|
|
|
U3En\HG |
WORD |
Decimal |
Available |
|
|
|
U3En\HG |
BIT |
Decimal |
Available |
Bit specification |
|
|
X |
BIT |
Hexadecimal |
Available |
|
|
|
Y |
BIT |
Hexadecimal |
Available |
|
1 We do not recommend using combinations of register name and assignable data type that are not listed in this table.